Computer Architecture

• E.T

  2013-06-20
  A difficult decision is whether to make the cache hit time fast, to keep pace with the high clock rate of processors, or to make the cache large to reduce the gap between the processor accesses and main memory accesses. Adding another level of cache between the original cache and memory simplifies the decision (see Figure 2.3). The first-level cache can be small enough to match a fast clock cycle time, yet the second-level (or third-level) cache can be large enough to capture many accesses that would go to main memory. The focus on misses in second-level caches leads to larger blocks, bigger capacity, and higher associativity. Multilevel caches are more power efficient than a single aggregate cache.
• 容貌焦虑主理人

  2013-04-16
  四插槽MD四插槽AMD
• 容貌焦虑主理人

  2013-04-16
  (2) 存储器寻址。80x86（见附录图A-2）不需要对齐，但如果操作数是对齐的，访问速度通常会更快一些。(See Figure A.5 on page A-8.) The 80x86 does not requirealignment, but accesses are generally faster if operands are aligned.（见附录A图A.5）
• 容貌焦虑主理人

  2013-04-11
  1.10Putting It All Together: Performance, Price,and Power personal mobile devices (PMDs)
• [已注销]

  2012-09-07
  在设计上必须有所取舍时，一定要优先考虑较常发生的事件
• C55x

  2012-01-27
  The Google rule of thumb is currently to use the low-end range of server class computers.
• C55x

  2012-01-27
  How do WSCs compare to conventional datacenters?
• C55x

  2012-01-27
  The HPC clusters also tend to have long-running jobs that keep the server fully utilized, even for weeks at a time, while the utilization of servers in WSCs ranges between 10% and 50% and varies every day.
• C55x

  2012-01-27
  A natural question is whether WSCs are similar to modern clusters for high-performance computing. Although some have similar scale and cost...
• 松仓

  2012-02-13
  Measuring performance of multiprocessors by linear speedup versus execution time.