计算机组成与设计：硬件/软件接口 MIPS版（原书第6版）

• 发表：2024-07-31
• 分类：学习教育
• 围观：65

• 魏自新自律

  2023-12-27
  非常好，非常有趣。读了300多页，感觉得回来二刷了，东西比较多碎。处理器，寄存器，高速缓冲存储器。一个一个弄懂麻烦一些。

• 偏扁豆

  2024-10-27
  DRAM：动态随机访问存储器，集成电路形式的存储器，可随机访问任何地址的存储内客。访问时间大约为50ns，在2012年时每gigabyte售价5~10美元。cache：一种小而快的存储器，一般作为大而慢的存储器的缓存。cache使用SRAM。SRAM：静态随机访问存储器，集成电路形式的存储器比DRAM速度更快，集成度更低。随机访问代表访问数据的效率是O(1)
• 7086

  2022-01-11
  For example, as Figure 4.34 shows, the instruction memory is used during only one of the five stages of an instruction, allowing it to be shared by following instructions during the other four stages. To retain the value of an individual instruction for its other four stages, the value read from instruction memory must be saved in a register. Similar arguments apply to every pipeline stage, so we must place registers wherever there are dividing lines between stages in Figure 4.33. Returning to our laundry analogy, we might have a basket between each pair of stages to hold the clothes for the next step.
• 7086

  2022-01-10
  One popular approach to dynamic prediction of branches is keeping a history for each branch as taken or untaken, and then using the recent past behavior to predict the future. As we will see later, the amount and type of history kept have become extensive, with the result being that dynamic branch predictors can correctly predict branches with more than 90% accuracy(see Section 4.8). When the guess is wrong, the pipeline control must ensure that the instructions following the wrongly guessed branch have no effect and must restart the pipeline from the proper branch address.

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